LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 130
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
Number
GND
GND
GND
AA1
AB1
AC1
AB2
AA2
AA3
Ball
W1
W2
W6
W3
W4
W5
R5
U1
U2
R6
U5
U3
U4
U7
U6
P5
P6
T3
T4
T5
T6
V1
V2
V4
V5
V3
V6
Y1
Y2
Y4
Y3
Y5
-
Function
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
GND6
GND6
GND6
VCCJ
TCK
TMS
TDO
Ball
TDI
NC
NC
NC
NC
-
LFEC20/LFECP20
Bank LVDS
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_IN_A
Dual Function
LDQS36
LDQS45
4-64
Number
GND
GND
GND
GND
AA1
AB1
AC1
AB2
AA2
AA3
Ball
W1
W2
W6
W3
W4
W5
P5
P6
R5
U1
U2
R6
U5
U3
U4
V1
V2
U7
V4
V5
V3
U6
V6
Y1
Y2
Y4
Y3
Y5
T3
T4
T5
T6
Function
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
PL48A
PL48B
PL49A
PL49B
PL50A
PL50B
PL51A
PL51B
PL53A
PL53B
PL54A
PL54B
PL55A
PL55B
PL56A
PL56B
PL57A
PL57B
PL58A
PL58B
PL59A
PL59B
PL60A
PL60B
PL61A
PL61B
GND6
GND6
GND6
GND6
VCCJ
TMS
TDO
TCK
Ball
LatticeECP/EC Family Data Sheet
TDI
LFECP/EC33
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
LLM0_PLLC_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLT_IN_A
Function
LDQS48
LDQS57
Dual
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