LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 100
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA
Number
GND
GND
GND
GND
M13
M14
M15
M16
Ball
R15
R16
N16
N15
H16
H15
G16
G15
H13
H14
G14
H12
P14
P15
P16
L16
K16
L12
L14
L13
K13
L15
K15
K14
K12
F16
F15
E16
E15
J16
J12
J14
J15
J13
-
Ball Function
PROGRAMN
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR18B
DONE
GND3
GND3
GND3
GND2
CFG2
CFG1
CFG0
CCLK
INITN
-
Bank
LFECP10/LFEC10
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
-
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
DI/CSSPIN
PCLKC2_0
D7/SPID0
RDQS33
RDQS24
4-34
Ball Function
PROGRAMN
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
DONE
GND3
CFG2
CFG1
CFG0
CCLK
GND3
GND3
GND3
GND2
INITN
LatticeECP/EC Family Data Sheet
Bank
LFECP15/LFEC15
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
DI/CSSPIN
PCLKC2_0
D7/SPID0
RDQS41
RDQS28
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