LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 28
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LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-29. Output Register Block
Figure 2-30. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Routing
From
ONEG0
OPOS0
CLK1
*Latch is transparent when input is low.
CLK
LSR
DA
DB
/LATCH
D
D
D-Type
LE*
Latch
ODDRXB
2-25
Q
Q
Q
0
1
LatticeECP/EC Family Data Sheet
Programmed
Control
OUTDDN
0
1
To sysIO
Buffer
DO
Architecture
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