LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 25
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LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Table 2-12. PIO Signal List
Figure 2-25. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
CE0, CE1
CLK0, CLK1
LSR
GSRN
INCK
DQS
INDD
INFF
IPOS0, IPOS1
ONEG0
OPOS0,
OPOS1 ONEG1
TD
DDRCLKPOL
Name
Control from the core
Control from the core
Control from the core
Control from routing
Input to the core
Input to PIO
Input to the core
Input to the core
Input to the core
Control from the core
Control from the core
Tristate control from the core
Tristate control from the core
Control from clock polarity bus
DQS
Type
Clock enables for input and output block FFs.
System clocks for input and output blocks.
Local Set/Reset.
Global Set/Reset (active low).
Input to Primary Clock Network or PLL reference inputs.
DQS signal from logic (routing) to PIO.
Unregistered data input to core.
Registered input on positive edge of the clock (CLK0).
DDRX registered inputs to the core.
Output signals from the core for SDR and DDR operation.
Output signals from the core for DDR operation
Signals to Tristate Register block for DDR operation.
Tristate signal from the core used in SDR operation.
Controls the polarity of the clock (CLK0) that feed the DDR input block.
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-22
Buffer
Delay
sysIO
LatticeECP/EC Family Data Sheet
Description
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADA "T"
PADB "C"
Assigned
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture
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