LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 128
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA
Number
GND
GND
Ball
D5
C3
D3
C2
C1
G3
D2
D1
G2
G6
H4
G4
H6
G5
H5
H3
H2
E3
E4
E5
F4
F5
B2
B1
F3
E2
E1
F2
F6
K4
K5
J7
J3
J2
J4
J5
J6
-
-
-
Function
PL11A
PL11B
PL12A
PL12B
PL13A
GND7
GND7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
Ball
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
-
-
-
LFEC20/LFECP20
Bank LVDS
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
LUM0_PLLC_FB_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
LUM0_PLLT_IN_A
Dual Function
VREF2_7
VREF1_7
LDQS6
4-62
Number
GND
GND
GND
GND
GND
Ball
G3
G2
G6
G4
G5
E3
E4
E5
D5
C3
D3
C2
B2
B1
C1
D2
E2
D1
E1
H4
H6
H5
H3
H2
K4
K5
F4
F5
F3
F2
F6
J7
J3
J2
J4
J5
J6
Function
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
PL23B
PL24A
PL24B
PL25A
GND7
GND7
GND7
GND7
GND7
PL2A
PL2B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
Ball
LatticeECP/EC Family Data Sheet
LFECP/EC33
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
LUM0_PLLC_FB_A
LUM0_PLLT_FB_A
LUM0_PLLC_IN_A
LUM0_PLLT_IN_A
VREF2_7
VREF1_7
Function
LDQS14
LDQS23
LDQS6
Dual
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