LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 163
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
September 2005
November 2005
November 2007
February 2007
February 2008
January 2007
March 2006
May 2007
Date
Version
02.0
02.1
02.2
02.3
02.4
02.5
02.6
02.7
Ordering Information
Pinout Information
Pinout Information
DC & Switching
DC & Switching
DC & Switching
DC & Switching
DC & Switching
Characteristics
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Architecture
Architecture
Architecture
Architecture
Information
Section
sysIO section has been updated.
Recommended Operating Conditions has been updated with V
DC Electrical Characteristics table has been updated
Removed 5V Tolerant Input Buffer section.
Register-to-Register performance table has been updated (rev. G 0.28).
LatticeECP/EC External Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Internal Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28).
sysCLOCK PLL timing table has been updated (rev. G 0.28)
LatticeECP/EC sysCONFIG Port Timing specification table has been
updated (rev. G 0.28).
Master Clock table has been updated (rev. G 0.28).
JTAG Port Timing specification table has been updated (rev. G 0.28).
Signal Description table has been updated with V
Pin-to-Pin Performance table has been updated (G 0.30)
- 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX
Register-to-Register Performance (G 0.30) - No timing number
changes.
External Switching Characteristics (G 0.30) - No timing number
changes.
Internal Switching Characteristics (G 0.30)
-t
have been updated.
Family Timing Adders (G 0.30) - No timing number changes.
sysCLOCK PLL Timing (G 0.30) - No timing number changes.
sysCONFIG Port Timing Specifications (G 0.30) - No timing number
changes.
Master Clock (G 0.30) - No timing number changes.
JTAG Port Timing Specification (G 0.30) - No timing number changes.
Added 208-PQFP lead-free part numbers.
Added footnote 3. to V
tions table.
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated Maximum Number of Elements in a Block table - MAC value
for x9 changed to 2.
Updated text in Ripple Mode section.
Added JTAG Port Waveforms diagram.
Updated t
Added Thermal Management text section.
Updated title list.
Read/Write Mode (Normal) and Read/Write Mode with Input and Output
Registers waveforms in the EBR Memory Timing Diagrams section
have been updated.
SUP_DSP,
7-3
RST
t
HP_DSP
timing information in the sysCLOCK PLL Timing table.
, t
SUO_DSP,
CCAUX
LatticeECP/EC Family Data Sheet
Change Summary
in the Recommended Operating Condi-
t
HO_DSP,
t
COI_DSP
, t
Revision History
COD_DSP
CCPLL
.
numbers
CCPLL
.
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