LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 49
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Derating Timing Tables
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be
much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and
voltage multiply the noted numbers with the derating factors provided below.
The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-
acteristics (Θ
The user must determine this temperature and then use it to determine the derating factor based on the following
derating tables: T
Table 3-5. Delay Derating Table for Internal Blocks
JA
), and the ambient temperature, as calculated with the following equation:
J
°C.
Commercial
T
J
—
—
25
85
0
°C
Industrial
T
T
105
-40
-25
J
20
45
JMAX
°C
= T
AMAX
1.14V
3-13
0.82
0.82
0.89
0.93
1.00
+ (Power * Θ
Power Supply Voltage
1.2V
0.77
0.76
0.83
0.87
0.94
JA
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
)
1.26V
0.71
0.71
0.78
0.81
0.89
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