WI.232FHSS-250-R Radiotronix, WI.232FHSS-250-R Datasheet - Page 42

• Manufacturer Part Number: WI.232FHSS-250-R
• Description: RF Modules & Development Tools 900MHz FHSS Low
• Manufacturer: Radiotronix

Specifications of WI.232FHSS-250-R

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: WI232FHSS-250-R

WI.232FHSS-25-R/ WI.232FHSS-250-R DATASHEET
Default UART Acknowledge on Wake: Enabled (0x01)
When UART Acknowledge on Wake is enabled, the module will send an ACK (0x06) character out of the
UART TxD pin after the module wakes. This indicates that the module is ready to accept data and
command traffic. A value of 0x01 enables this feature. Setting the register to 0x00 disables it.
Default User Destination ID[3]: 0xFF
This is the most significant byte (byte 3) of the 32-bit user extended destination address. When Extended
User addressing is enabled, this register is used in conjunction with User Destination Address[2-0]
registers to direct a transmitted packet to the proper endpoint(s). For more information on the operation of
addressing modes, please refer to the
Default User Destination ID[2]: 0xFF
This is byte 2 of the 32-bit user extended destination address. When Extended User addressing is enabled,
this register is used in conjunction with User Destination ID[3] and User Destination ID[1-0] registers to
direct a transmitted packet to the proper endpoint(s). For more information on the operation of addressing
modes, please refer to the
R/W
D7
7
R/W
D7
7
R/W
D7
7
R/W
D7
7
4.1.13. UART Acknowledge on Wake (regACKONWAKE)
4.1.14. User Destination ID[3] (regUSERDESTID[3])
4.1.15. User Destination ID[2] (regUSERDESTID[2])
4.1.16. User Destination ID[1] (regUSERDESTID[1])
regNVUSERDESTID[3] (0x0F)
regNVUSERDESTID[2] (0x10)
regNVUSERDESTID[1] (0x11)
regNVACKONWAKE (0x0E)
R/W
D6
6
R/W
D6
6
R/W
D6
6
R/W
D6
6
Addressing Modes
R/W
D5
5
R/W
D5
5
R/W
D5
5
R/W
D5
5
Addressing Modes
R/W
D4
4
R/W
D4
4
R/W
D4
4
R/W
D4
4
section of this document.
41
D3
3
D3
3
D3
3
D3
3
R/W
R/W
R/W
R/W
section of this document.
R/W
D2
2
R/W
D2
2
R/W
D2
2
R/W
D2
2
regUSERDESTID[3] (0x5A)
regUSERDESTID[2] (0x5B)
regUSERDESTID[1] (0x5C)
regACKONWAKE (0x59)
R/W
D1
1
R/W
D1
1
R/W
D1
1
R/W
D1
1
Revision 1.1.0
R/W
D0
0
R/W
D0
0
R/W
D0
0
R/W
D0
0