SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 253

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
23.1.1.2. TX State
The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to tran-
sition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of
events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit.
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to
setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled.
23.1.1.3. RX State
The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to tran-
sition from one of the IDLE modes to the RX state. The following sequence of events will occur automati-
cally to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit:
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable receive circuits: LNA, mixers, and ADC.
7. Enable receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed auto-
matically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet
handling (optional) including sync word, header check, and CRC.
23.1.1.4. Device Status
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
02
R
Device Status
ffovfl
ffunfl
rxffem
headerr
freqerr
cps[1] cps[0]
—
The operational status of the EZRadioPRO peripheral can be read from "Register 02h. Device Status".
23.2. Interrupts
The EZRadioPRO peripheral is capable of generating an interrupt signal (nIRQ) when certain events
occur. The nIRQ pin is driven low to indicate a pending interrupt request. The EZRadioPRO interrupt
does not have an internal interrupt vector. To use the interrupt, the nIRQ pin must be looped back
to an external interrupt input. This interrupt signal will be generated when any one (or more) of the inter-
rupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low
until the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit is read.
The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be
Rev. 1.0
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