ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 24

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020
Internal AFC
The ADF7020 supports a real-time internal automatic
frequency control loop. In this mode, an internal control
loop automatically monitors the frequency error and adjusts
the synthesizer N divider using an internal PI control loop.
The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered,
based on the crystal frequency in use. This is set up in
Bits R11_DB[4:19] and should be calculated using
Therefore, using a 10 MHz XTAL yields an AFC scaling
coefficient of 839.
AFC Performance
The improved sensitivity performance of the Rx when AFC is
enabled and in the presence of frequency errors is shown in
Figure 18. The maximum AFC frequency range is ±50 kHz,
which corresponds to ±58 ppm at 868 MHz. This is the total
error tolerance allowed in the link. For example, in a point-to-
point system, AFC can compensate for two ±29 ppm crystals or
one ±50 ppm crystal and one ±8 ppm TCXO.
AFC settling typically takes 48 bits to settle within ±1 kHz. This
can be improved by increasing the postdemodulator bandwidth
in Register 4 at the expense of Rx sensitivity.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensi-
tivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB[22:23].
AFC_Scaling_Coefficient = (500 × 2
24
)/ XTAL
Rev. B | Page 24 of 48
AUTOMATIC SYNC WORD RECOGNITION
The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7020. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational require-
ments of the microprocessor and reduces the overall power
consumption. The INT/LOCK is automatically deasserted again
after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by
selecting Demodulator Mode 2 or Demodulator Mode 3 in the
demodulator setup register. Do this by setting Bits R4_DB[25:23] =
010 or 011. Bits R5_DB[4:5] are used to set the length of the
sync/ID word, which can be 12, 16, 20, or 24 bits long. The
transmitter must transmit the MSB of the sync byte first and the
LSB last to ensure proper alignment in the receiver sync byte
detection hardware.
For systems using forward error correction (FEC), an error
tolerance parameter can also be programmed that accepts a
valid match when up to three bits of the word are incorrect. The
error tolerance value is assigned in Bits R5_DB[6:7].