ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 23

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 9. Register Settings
Setting Name
Postdemod_BW_Setting
Discriminator_BW
Dot_Product
RxData_Invert
1
LINEAR FSK DEMODULATOR
Figure 31 shows a block diagram of the linear FSK demodulator.
This method of frequency demodulation is useful when very
short preamble length is required, and the system protocol
cannot support the overhead of the settling time of the internal
feedback AFC loop settling.
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu-
lated FSK data is recovered by threshold-detecting the output of
the averaging filter, (see Figure 31). In this mode, the slicer
output shown in Figure 31 is routed to the data synchronizer
PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB[4:5] to 00.
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB[6:15] and is defined as
where f
postdemodulator filter. DEMOD_CLK is as defined in the
Register 3—Receiver Clock Register section, second comment.
LIMITER
ADC RSSI OUTPUT
Q
The latest version of the ADF7020 configuration software can aid in
calculating register settings.
I
Figure 31. Block Diagram of Frequency Measurement System and
Postdemod
CUTOFF
LINEAR DISCRIMINATOR
LEVEL
FREQUENCY
is the target 3 dB bandwidth in Hz of the
IF
_
ASK/OOK/Linear FSK Demodulator
BW
_
Setting
7
1
MUX 1
=
Register Address
R4_DB[6:15]
R6_DB[4:13]
R6_DB14
R6_DB29
R4_DB[6:15]
2
DEMOD
10
×
2
π
×
f
_
CUTOFF
CLK
FREQUENCY
READBACK
AND
AFC LOOP
SLICER
Value
0x09
0x3F
0
1
RxDATA
Rev. B | Page 23 of 48
ASK/OOK Operation
ASK/OOK demodulation is activated by setting Bits R4_DB[4:5]
to 10.
Digital filtering and envelope detecting the digitized RSSI input
via MUX 1, as shown in Figure 31, performs ASK/OOK
demodulation. The bandwidth of the digital filter must be
optimized to remove any excess noise without causing ISI in the
received ASK/OOK signal.
The 3 dB bandwidth of this filter is typically set at approximately
0.75 times the user data rate and is assigned by R4 _DB[6:15] as
where f
postdemodulator filter.
It is also recommended to adjust the peak response factor to 6
in Register 10 for robust operation over the full input range.
This improves the receiver’s AM immunity performance.
AFC
The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches between
the transmit and receive crystals. This uses the frequency
discriminator block, as described in the Linear FSK Demodulator
section (see Figure 31). The discriminator output is filtered and
averaged to remove the FSK frequency modulation, using a
combined averaging filter and envelope detector. In FSK mode,
the output of the envelope detector provides an estimate of the
average IF frequency.
Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).
External AFC
The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizer’s N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_READBACK, as described in the Readback Format
section, and applying the following formula:
Note that while the AFC_READBACK value is a signed number,
under normal operating conditions, it is positive. The frequency
error can be calculated from
Thus, in the absence of frequency errors, the FREQ_RB value is
equal to the IF frequency of 200 kHz.
FREQ_RB [Hz] = ( AFC_READBACK × DEMOD_CLK )/2
FREQ_Error [Hz] = FREQ_RB (Hz) − 200 kHz
Postdemod
CUTOFF
is the target 3 dB bandwidth in Hz of the
_
BW
_
Setting
=
2
DEMOD
10
×
2
π
×
f
_
CUTOFF
CLK
ADF7020
15