ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 27

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
A dc-free preamble pattern is recommended for FSK/GFSK/
ASK/OOK demodulation. The recommended preamble pattern
is a dc-balanced pattern such as a 10101010… sequence.
Preamble patterns with longer run-length constraints such as
11001100… can also be used. However, this results in a longer
synchronization time of the received bit stream in the receiver.
The remaining fields that follow the preamble header do not
have to use dc-free coding. For these fields, the ADF7020 can
accommodate coding schemes with a run-length of up to
several bytes without any performance degradation, for example
several bytes of 0x00 or 0xFF. To help minimize bit errors when
receiving these long runs of continuous 0s or 1s, it is important
to choose a data rate and XTAL combination that minimizes
the error between the actual data rate and the on-board
CDR_CLK/32. For example, if a 9.6 kbps data rate is desired,
then using an 11.0592 MHz XTAL gives a 0% nominal error
between the desired data rate and CDR_CLK/32. AN-915 gives
more details on supporting long run lengths on the ADF7020.
The ADF7020 can also support Manchester-encoded data for
the entire protocol. Manchester decoding needs to be done on
the companion microcontroller, however. In this case, the
ADF7020 should be set up at the Manchester chip or baud
rate, which is twice the effective data rate.
PREAMBLE
Figure 35. Image Rejection Variation with Temperature after Initial
60
50
40
30
20
10
0
–60
V
IF BW = 25kHz
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
f
LEVEL= –100dBm
DEV
PRBS9
DD
Figure 36. Typical Format of a Transmit Protocol
= 3.0V
= 4kHz
–40
Calibrations at +25°C, −40°C, and +85°C
CAL AT +85°C
WORD
SYNC
–20
TEMPERATURE (°C)
FIELD
0
ID
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
f
DEV
CAL AT +25°C
PRBS11
20
= 4kHz
DATA FIELD
40
CAL AT –40°C
60
80
CRC
100
Rev. B | Page 27 of 48
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
Table 10 lists the minimum number of writes needed to set up
the ADF7020 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection or
enabling AFC. When going from Tx to Rx or vice versa, the
user needs to write only to the N Register to alter the LO by
200 kHz and to toggle the Tx/Rx bit.
Table 10. Minimum Register Writes Required for Tx/Rx Setup
Mode
Tx
Rx (OOK)
Rx (G/FSK)
Tx ↔Rx
Figure 39 and Figure 40 show the recommended programming
sequence and associated timing for power-up from standby mode.
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing the
ADF7020 to the Analog Devices
microcontrollers, or the
hardware connections shown in Figure 37 and Figure 38.
ADSP-BF533
ADuC84x
GPIO
Figure 38. ADSP-BF533 to ADF7020 Connection Diagram
P3.2/INT0
Figure 37. ADuC84x to ADF7020 Connection Diagram
SCLOCK
RSCLK1
DR1PRI
DT1PRI
V
DDEXT
MISO
MOSI
MOSI
MISO
RFS1
GND
Register
Reg. 0
Reg. 0
Reg. 0
Reg. 0
P3.7
P2.4
P2.5
P2.6
P2.7
SCK
PF5
PF6
SS
Black fin ®
Reg. 1
Reg. 1
Reg. 1
ADuC84x
ADSP-BF53x DSPs, using the
Reg. 2
Reg. 3
Reg. 3
analog
DATA I/O
DATA CLK
CE
INT/LOCK
SREAD
SLE
SDATA
SCLK
SCLK
SDATA
SREAD
SLE
DATA CLK
DATA I/O
INT/LOCK
CE
VDD
GND
Reg. 4
Reg. 4
ADF7020
ADF7020
ADF7020
Reg. 6
Reg. 6