ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 31

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

SERIAL INTERFACE
The serial interface allows the user to program the fourteen
32-bit registers using a 3-wire interface (SCLK, SDATA, and
SLE). Signals should be CMOS compatible. The serial interface
is powered by the regulator and, therefore, is inactive when
CE is low.
Data is clocked into the register, MSB first, on the rising edge
of each clock (SCLK). Data is transferred to one of fourteen
latches on the rising edge of SLE. The destination latch is
determined by the value of the four control bits (C4 to C1).
These are the bottom four LSBs, DB3 to DB0, as shown in the
timing diagram in Figure 3.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin (see Figure 42), starting with the MSB first. The
data appearing at the first clock cycle following the latch
operation must be ignored. The last (eighteenth) SCLK edge
puts the SREAD pin back in three-state.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprising Bit RV1 to Bit RV16 and is scaled according to the
following formula:
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that, for the AFC readback
to yield a valid result, the down-converted input signal must not
fall outside the bandwidth of the analog IF filter. At low input
signal levels, the variation in the readback value can be improved
by averaging.
FREQ_RB [Hz] = ( AFC_READBACK × DEMOD_CLK )/2
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
FILTER CAL READBACK
READBACK MODE
SILICON REVISION
RSSI READBACK
AFC READBACK
DB15
RV16
RV16
X
X
0
DB14
RV15
RV15
X
X
0
DB13
RV14
RV14
X
X
0
DB12
RV13
RV13
X
X
0
Figure 42. Readback Value Table
DB11
RV12
RV12
X
X
0
Rev. B | Page 31 of 48
15
DB10
RV11
RV11
LG2
X
0
RV10
RV10
DB9
LG1
X
0
READBACK VALUE
RSSI Readback
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 42. It comprises the RSSI level information
(Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the
current LNA gain (LG1, LG2) setting. The filter and LNA gain
are coded in accordance with the definitions in Register 9. With
the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC section.
Battery Voltage/ADCIN/Temperature Sensor Readback
These three ADC readback values are valid by just enabling the
ADC in Register 8 without writing to the other registers. The
battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery, ADCIN voltage or temperature can be obtained using
Silicon Revision Readback
The silicon revision word is coded with four quartets in BCD
format. The product code (PC) is coded with three quartets
extending from Bit RV5 to Bit RV16. The revision code (RV) is
coded with one quartet extending from Bit RV1 to Bit RV4. The
product code for the ADF7020 should read back as PC = 0x200.
The current revision code should read as RV = 0x8.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8 and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended. Before filter calibration is initiated, decimal 32
should be read back as the default value.
DB8
RV9
FG2
RV9
X
0
V
V
Temperature =
−40°C + (68.4 − Temperature_Sensor_Readback ) × 9.32
BATTERY
ADCIN
DB7
RV8
FG1
RV8
RV8
X
= ( ADCIN_Voltage_Readback )/42.1
DB6
RV7
RV7
RV7
RV7
RV7
= ( Battery_Voltage_Readback )/21.1
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
DB0
RV1
RV1
RV1
RV1
RV1
ADF7020