ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 11

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 18
19, 22
20, 21, 23
24
25
26
Mnemonic
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
VDD4
RSET
CREG4
GND4
MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
GND4
FILT_Q, FILT_Q,
TEST_A
CE
SLE
SDATA
LNA
Description
The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as
possible to this pin. All VDD pins should be tied together.
The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
Ground for Output Stage of Transmitter. All GND pins should be tied together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
Complementary LNA Input. See the LNA/PA Matching section.
External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5%
tolerance.
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND
for regulator stability and noise rejection.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the fourteen latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
RFGND
CREG1
RFOUT
CREG4
VCOIN
RFINB
GND4
VDD1
VDD4
RSET
R
RFIN
LNA
10
11
12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 6. Pin Configuration
Rev. B | Page 11 of 48
(Not to Scale)
ADF7020
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
CLKOUT
DATA CLK
DATA I/O
INT/LOCK
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
ADF7020