ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 21

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integra-
tor in feedback around the log amp. This uses the baseband
offset clock divide. The RSSI level is converted for user
readback and digitally controlled AGC by an 80-level (7-bit)
flash ADC. This level can be converted to input power in dBm.
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain
is reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed
to allow for settling of the loop. The user programs the two
threshold values (recommended defaults of 30 and 70) and the
delay (default of 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz.
where BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information and Timing
AGC is selected by default, and operates by selecting the appropri-
ate LNA and filter gain settings for the measured RSSI level. It
is possible to disable AGC by writing to Register 9 if entering
one of the modes listed in Table 5 is desired, for example. The
time for the AGC circuit to settle and, therefore, the time to
take an accurate RSSI measurement is typically 150 μs, although
this depends on how many gain settings the AGC circuit has to
cycle through. After each gain change, the AGC loop waits for
a programmed time to allow transients to settle.
NOTES
1. FWR = FULL WAVE RECTIFIER
BBOS_CLK (Hz) = XTAL /( BBOS_CLK_DIVIDE )
1
FWR
CORRECTION
A
OFFSET
FWR
Figure 29. RSSI Block Diagram
A
R
FWR
A
FWR
LATCH
CLK
FSK
DEMOD
ADC
RSSI
ASK
DEMOD
Rev. B | Page 21 of 48
This wait time can be adjusted to speed up this settling by
adjusting the appropriate parameters.
Thus, in the worst case, if the AGC loop has to go through all
5 gain changes, AGC_Delay =10, SEQ_CLK = 200 kHz, AGC
Settling = 10 × 5 μs × 5 = 250 μs. Minimum AGC_Wait_Time
needs to be at least 25 μs.
RSSI Formula (Converting to dBm)
where:
Readback_Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
Gain_Mode_Correction is given by the values in Table 6.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also
obtained from the readback register.
Table 6. Gain Mode Correction
LNA Gain
(LG2, LG1)
H (1,1)
M (1,0)
M (1,0)
M (1,0)
L (0,1)
EL (0,0)
An additional factor should be introduced to account for losses
in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020
The two FSK demodulators on the ADF7020 are
•
•
Select these using the demodulator select bits, R4_DB[4:5].
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + f
(IF − f
from each of the two correlators. The performance of this fre-
quency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in
the presence of additive white Gaussian noise (AWGN).
AGC Settling = AGC_Wait_Time × Number of Gain Changes
Input_Power [dBm] = −120 dBm + ( Readback_Code +
Gain_Mode_Correction ) × 0.5
FSK correlator/demodulator
Linear demodulator
AGC
AGC
DEV
). Data is recovered by comparing the output levels
_
_
Wait
DELAY
XTAL
_
Filter Gain
(FG2, FG1)
H (1,0)
H (1,0)
M (0,1)
L (0,0)
L (0,0)
L (0,0)
Time
×
SEQ
=
_
CLK
Gain Mode Correction
0
24
45
63
90
105
ADF7020
DEV
) and