ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 16

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020
Voltage Regulators
The ADF7020 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
CREGx and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the chip-enable pin low disables the
regulators, reduces the supply current to less than 1 μA, and
erases all values held in the registers. The serial interface
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (CREG4) can be monitored using
the regulator ready signal from MUXOUT.
Loop Filter
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 22.
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately one and a half times the data rate.
Widening the LBW excessively reduces the time spent jumping
between frequencies, but it can cause insufficient spurious
attenuation.
For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels can result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW can
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.
For GFSK, it is recommended that an LBW of 1.0 to 1.5 times
the data rate be used to ensure that sufficient samples are
taken of the input data while filtering system noise. The free
design tool
filters for the ADF7020. It can also be used to view the effect of
loop filter bandwidth on the spectrum of the transmitted signal
for different combinations of modulation type, data rates, and
modulation indices.
PUMP OUT
ADI SRD Design Studio™
CHARGE
Figure 22. Typical Loop Filter Configuration
can be used to design loop
VCO
Rev. B | Page 16 of 48
N Counter
The feedback divider in the ADF7020 PLL consists of an 8-bit
integer counter and a 15-bit Σ-Δ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as
The maximum N divide value is the combination of the
Integer_N (maximum = 255) and the Fractional_N (maximum
= 32767/32768) and puts a lower limit on the minimum
usable PFD.
PFD
For example, when operating in the European 868 MHz to
870 MHz band, PFD
cases, it is advisable to use as high a value of PFD as possible
to obtain best phase noise performance.
Voltage Controlled Oscillator (VCO)
To minimize spurious emissions, the on-chip VCO operates
from 1724 MHz to 1912 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO Adjust Bits
R1_DB[20:21].
The VCO is enabled as part of the PLL by the PLL Enable bit,
R0_DB28.
A further frequency divide-by-2 block is included to allow
operation in the lower 433 MHz and 460 MHz bands. To enable
operation in these bands, R1_DB13 should be set to 1. The
VCO needs an external 22 nF between the VCO and the
regulator to reduce internal noise.
MIN
REFERENCE IN
f
OUT
[Hz] = Maximum Required Output Frequency /(255 + 1)
4÷R
=
PFD
CHARGE
FRACTIONAL-N
×
PUMP
PFD/
⎛
⎜
⎝
Integer
MIN
Figure 23. Fractional-N PLL
equals 3.4 MHz. In the majority of
_
Σ-Δ MODULATOR
THIRD-ORDER
N
+
Fractional
2
15
INTEGER-N
_
VCO
4÷N
N
⎞
⎟
⎠