ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 46

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

8.1.1.2 PHY Header (PHR)
8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)
8.1.2 MAC Protocol Layer Data Unit (MPDU)
8.1.2.1 MAC Header (MHR) Fields
8.1.2.2 Frame Control Field (FCF)
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AT86RF230
The PHY header consists of a single octet following the SHR. The least significant
7 bits of that octet denote the frame length of the following PSDU, while the most
significant bit of that octet is reserved.
During transmission, the PHR field has to be supplied by the microcontroller during
Frame Buffer write access.
On receive, the radio transceiver does not write the PHR field into the Frame Buffer.
Instead it is prefixed to the PSDU during Frame Buffer read access. Note, that the
reserved MSB of the PHR octet is always set to 0.
The PSDU has a variable length between one and 127 octets.
The MAC header consists of the Frame Control Field (FCF), a sequence number, and
the variable length addressing fields.
The FCF consists of 16 bits, and occupies the first two octets of the MPDU.
Bit [2:0] describe the frame type. Table 8-1 summarizes frame types defined by
IEEE 802.15.4-2003, section 7.2.1.1.1.
Table 8-1. IEEE 802.15.4-2003 Frame Types
These bits are used for address filtering by applying the IEEE 802.15.4-2003 third level
filter rules. Only frame types 0 – 3 pass the third level filter rules. Automatic address
filtering by the AT86RF230 is enabled when using the RX_AACK operation (see section
7.2.3.1).
Bit 3: indicates whether security processing applies to this frame. This field is not
evaluated by the AT86RF230.
Bit 4 is the “frame pending” subfield. This field can be set in an acknowledgement
frame. It indicates that the transmitter of the acknowledgement frame has more data to
send for the recipient of the acknowledgement frame. For acknowledgment frames
automatically generated by the AT86RF230, this bit is set according to the content of
register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1).
Bit 5 forms the “acknowledgment request” subfield. If this bit is set within a data or MAC
command frame that is not broadcast, the recipient shall acknowledge the reception of
the frame within the time specified by IEEE 802.15.4-2003 (i.e. within 192 µs for
Frame Control field bit assignments
100 – 111
Bit [2:0]
000
001
010
011
value
4 – 7
0
1
2
3
Description
Beacon
Data
Acknowledge
MAC command
Reserved
5131E-MCU Wireless-02/09