MC68HC908JB8JDW Freescale Semiconductor, MC68HC908JB8JDW Datasheet - Page 189

• Manufacturer Part Number: MC68HC908JB8JDW
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11.9 I/O Signals
11.9.1 TIM Clock Pin (PTE0/TCLK)
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
11.10 I/O Registers
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Port E shares three of its pins with the TIM. PTE0/TCLK is an external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/TCH0 and PTE2/TCH1.
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See
TCLK pulse width, TCLK
The maximum TCLK frequency is:
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0 can be configured as
buffered output compare or buffered PWM pins.
The following I/O registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
Timer Interface Module (TIM)
11.10.1 TIM Status and Control
LMIN
------------------------------------ -
bus frequency
bus frequency ÷ 2
or TCLK
1
HMIN
+
, is:
t
SU
Register.) The minimum
Timer Interface Module (TIM)
Technical Data
I/O Signals
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