MC68HC908JB8JDW Freescale Semiconductor, MC68HC908JB8JDW Datasheet - Page 128

• Manufacturer Part Number: MC68HC908JB8JDW
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Universal Serial Bus Module (USB)
9.5.1.3 Address Field (ADDR)
9.5.1.4 Endpoint Field (ENDP)
9.5.1.5 Cyclic Redundancy Check (CRC)
9.5.1.6 End-of-Packet (EOP)
Technical Data
128
The address field is a 7-bit number that is used to select a particular USB
device. This field is compared to the lower seven bits of the UADDR
register to determine if a given transaction is targeting the MCU USB
device.
The endpoint field is a 4-bit number that is used to select a particular
endpoint within a USB device. For the MCU, this will be a binary number
between 0 and 2 inclusive. Any other value will cause the transaction to
be ignored.
Cyclic redundancy checks are used to verify the address and data
stream of a USB transaction. This field is five bits wide for token packets
and 16 bits wide for data packets. CRCs are generated in the transmitter
and sent on the USB data lines after both the endpoint field and the data
field.
The single-ended 0 (SE0) state is used to signal an end-of-packet
(EOP). The single-ended 0 state is indicated by both D+ and D– being
below 0.8V. EOP will be signaled by driving D+ and D– to the
single-ended 0 state for two bit times followed by driving the lines to the
idle state for one bit time. The transition from the single-ended 0 to the
idle state defines the end of the packet. The idle state is asserted for one
bit time and then both the D+ and D– output drivers are placed in their
high-impedance state. The bus termination resistors hold the bus in the
idle state.
end-of-packet transaction.
Universal Serial Bus Module (USB)
Figure 9-7
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
shows the data signaling and voltage levels for an
Freescale Semiconductor