CY7C60223-PXC Cypress Semiconductor Corp, CY7C60223-PXC Datasheet - Page 55

• Manufacturer Part Number: CY7C60223-PXC
• Description: IC MCU 8K WIRELESS 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™ II CY7C602xxr

Specifications of CY7C60223-PXC

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: LVD, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY3216 - KIT PROGRAMMER MODULAR428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 428-1797

19.1 Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in
remains posted until the interrupt is taken or until it is cleared by
writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
19.2 Interrupt Processing
The sequence of events that occur during interrupt processing is
as follows:
Document 38-16016 Rev. *F
1. An interrupt becomes active, either because:
2. The current executing instruction finishes.
3. The internal interrupt is dispatched, taking 13 cycles. During
a. The interrupt condition occurs (for example, a timer expires).
b. A previously posted interrupt is enabled through an update
c. An interrupt is pending and GIE is set from 0 to 1 in the CPU
a. The MSB and LSB of Program Counter and Flag registers
b. The PCH, PCL, and Flag register (CPU_F) are stored onto
c. The CPU_F register is then cleared. Because this clears the
d. The PCH (PC[15:8]) is cleared to zero.
e. The interrupt vector is read from the interrupt controller and
this time, the following actions occur:
of an interrupt mask register.
Flag register.
(CPU_PC and CPU_F) are stored onto the program stack
by an automatic CALL instruction (13 cycles) generated
during the interrupt acknowledge process.
the program stack (in that order) by an automatic CALL
instruction (13 cycles) generated during the interrupt
acknowledge process.
GIE bit to 0, additional interrupts are temporarily disabled.
its value placed into PCL (PC[7:0]). This sets the program
counter to point to the appropriate address in the interrupt
table (for example, 0004h for the POR and LVD interrupt).
GPIO, etc.)
Interrupt
Source
(Timer,
Figure 19-1
1
INT_CLRx Write
Interrupt Taken
D
clocking in a ‘1’. The interrupt
or
R
Q
Figure 19-1. Interrupt Controller Block Diagram
Mask Bit Setting
Interrupt
INT_MSKx
Posted
Interrupt
Pending
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It simply prevents a
posted interrupt from becoming pending.
Nested interrupts are accomplished by reenabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register. A block diagram of the enCoRe II LV Interrupt
Controller is shown in
19.3 Interrupt Latency
The time between the assertion of an enabled interrupt and the
start of its ISR is calculated from the following equation.
Latency = Time for current instruction to finish + Time for internal
interrupt routine to execute + Time for LJMP instruction in
interrupt table to execute.
For example, if the 5 cycle JMP instruction is executing when an
interrupt becomes active, the total number of CPU clock cycles
before the ISR begins is as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)
+ (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 12 MHz, 25 clock cycles take 2.08 µs.
4. Program execution vectors to the interrupt table. Typically, a
5. The ISR executes. Note that interrupts are disabled because
6. The ISR ends with a RETI instruction, which restores the
7. Execution resumes at the next instruction, after the one that
LJMP instruction in the interrupt table sends execution to the
user's Interrupt Service Routine (ISR) for this interrupt.
GIE =0. In the ISR, interrupts are re-enabled if desired, by
setting GIE = 1 (avoid stack overflow).
Program Counter and Flag registers (CPU_PC and CPU_F).
The restored Flag register re-enables interrupts, because
GIE = 1 again.
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts are processed
before the next normal program instruction.
Encoder
Priority
CPU_F[0]
Figure
Interrupt Vector
CY7C601xx, CY7C602xx
GIE
19-1.
Interrupt
Request
M8C Core
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