CY7C60223-PXC Cypress Semiconductor Corp, CY7C60223-PXC Datasheet - Page 25

• Manufacturer Part Number: CY7C60223-PXC
• Description: IC MCU 8K WIRELESS 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™ II CY7C602xxr

Specifications of CY7C60223-PXC

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: LVD, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY3216 - KIT PROGRAMMER MODULAR428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 428-1797

Table 12-4. Clock I/O Configuration (CLKIOCR) [0x32] [R/W]
12.2.2 Interval Timer Clock (ITMRCLK)
The Interval Timer Clock (ITMRCLK) is sourced from the external
crystal oscillator, internal 24 MHz oscillator, internal 32 kHz low
power oscillator, or Timer Capture clock. A programmable
prescaler of 1, 2, 3, or 4 then divides the selected source. The
12-bit Programmable Interval Timer is a simple down counter
with a programmable reload value. It provides a 1 μs resolution
by default. When the down counter reaches zero, the next clock
is spent reloading. The reload value is read and written when the
counter is running, but ensure that the counter does not uninten-
tionally reload when the 12-bit reload value is only partially
stored—between two writes of the 12-bit value. The program-
mable interval timer generates an interrupt to the CPU on each
reload.
Document 38-16016 Rev. *F
Bit [7:5]: Reserved
Bit 4: XOSC Select
This bit, when set, selects the external crystal oscillator clock as clock source of external clock. When selecting the crystal
oscillator clock, first enable the crystal oscillator and wait for few cycles. This is the oscillator stabilization period. Then select
the crystal clock as clock source. Similarly, to deselect crystal clock, first deselect crystal clock as clock source then disable the
crystal oscillator.
0 = Not select external crystal oscillator clock.
1 = Select the external crystal oscillator clock.
Bit 3: XOSC Enable
This bit is only available on the CY7C601xx.
This bit when set enables the external crystal oscillator. The external crystal oscillator shares pads CLKIN and CLKOUT with
two GPIOs—P0.0 and P0.1 respectively. When the external crystal oscillator is enabled, the CLKIN signal comes from the
external crystal oscillator block and the output enables on the GPIOs for P0.0 and P0.1 are disabled, eliminating the possibility
of contention. When the external crystal oscillator is disabled, the source for CLKIN signal comes from the P0.0 GPIO input.
0 = Disable the external oscillator.
1 = Enable the external oscillator.
Note The external crystal oscillator startup time takes up to 2 ms.
Bit 2: EFTB Disabled
This bit is only available on the CY7C601xx.
0 = Enable the EFTB filter.
1 = Disable the EFTB filter, causing CLKIN to bypass the EFTB filter.
Bit [1:0]: CLKOUT Select
0 0 = Internal 24 MHz Oscillator
0 1 = External oscillator source
1 0 = Internal 32 kHz low power oscillator
1 1 = CPUCLK
Read/Write
Default
Field
Bit #
7
–
0
Reserved
6
–
0
5
–
0
XOSC
Select
R/W
4
0
The parameters to be set shows up on the device editor view of
PSoC Designer when you place the enCoRe II LV timer user
module.
PITIMER_Divider. The PITIMER_Source is the clock to the timer
and the PITIMER_Divider is the value the clock is divided by.
The interval register (PITMR) holds the value that is loaded into
the PIT counter on terminal count.
The programmable interval timer resolution is configurable. For
example:
TCAPCLK divide by x of CPU clock (for example TCAPCLK
divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 μs).
Enable
XOSC
R/W
3
0
The
parameters
Disabled
EFTB
R/W
CY7C601xx, CY7C602xx
2
0
are
R/W
1
0
CLKOUT Select
PITIMER_Source
Page 25 of 68
R/W
0
0
and
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