CY7C60223-PXC Cypress Semiconductor Corp, CY7C60223-PXC Datasheet - Page 32

• Manufacturer Part Number: CY7C60223-PXC
• Description: IC MCU 8K WIRELESS 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™ II CY7C602xxr

Specifications of CY7C60223-PXC

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: LVD, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY3216 - KIT PROGRAMMER MODULAR428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 428-1797

14.1 Sleep Sequence
The Sleep bit is an input into the sleep logic circuit. This circuit is
designed to sequence the device into and out of the hardware
sleep state. The hardware sequence to put the device to sleep
is shown in
The external crystal oscillator on enCoRe II LV devices is not
automatically powered down when the CPU enters the sleep
state. Firmware must explicitly disable the external crystal oscil-
lator to reduce power to levels specified.
Document 38-16016 Rev. *F
1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The
2. Due to the specific timing of the register write, the CPU issues
3. The system wide PD signal controls several major circuit
Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU
operation at an instruction boundary. The CPU samples BRQ
on the positive edge of CPUCLK.
a Bus Request Acknowledge (BRA) on the following positive
edge of the CPU clock. The sleep logic waits for the following
negative edge of the CPU clock and then asserts a system
wide Power Down (PD) signal. In
halted and the system wide power down signal is asserted.
blocks: the Flash memory module, the internal 24 MHz
oscillator, the EFTB filter, and the bandgap voltage reference.
These circuits transition into a zero power state. The only
operational circuits on chip are the low power oscillator, the
bandgap refresh circuit, and the supply voltage monitor
(POR/LVD) circuit.
Figure 14-1
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
CPUCLK
SLEEP
and is defined as follows.
BRQ
BRA
IOW
PD
Figure 14-1
CPU captures BRQ
on next CPUCLK
the CPU is
Figure 14-1. Sleep Timing
edge
responds with
14.1.1 Low Power in Sleep Mode
To achieve the lowest possible power consumption during
suspend or sleep, the following conditions are observed in
addition to considerations for the sleep timer and external crystal
oscillator:
■
■
■
■
All the other blocks go to the power down mode automatically on
suspend.
The following steps are user configurable and help in reducing
the average suspend mode power consumption.
For low power considerations during sleep when external clock
is used as the CPUCLK source, the clock source must be held
low to avoid unintentional leakage current. If the clock is held
high, then there may be a leakage through M8C. To avoid current
consumption make sure ITMRCLK and TCPCLK are not sourced
by either low power 32 kHz oscillator or 24 MHz crystal-less
oscillator. Do not select 24 MHz or 32 kHz oscillator clocks on to
the P01_CLKOUT pin.
1. Configure the power supply monitor at a large regular
2. Configure the low power oscillator into low power mode,
All GPIOs are set to outputs and driven low
Clear P11CR[0], P10CR[0]
Set P10CR[1]
Make sure the 32 kHz oscillator clock is not selected as clock
source to ITMRCLK, TCAPCLK, and not even as clock output
source onto P01_CLKOUT pin.
intervals, control register bits are 1,EB[7:6] (power system
sleep duty cycle PSSDC[1:0]).
control register bit is LOPSCTR[7].
a BRA
CPU
system clock is halted; the Flash
and bandgap are powered down
On the falling edge of CPUCLK,
PD is asserted. The 24/48 MHz
CY7C601xx, CY7C602xx
Page 32 of 68
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