EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 799
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 799 of 824
- Download datasheet (13Mb)
DS785UM1
28.2 Registers
When the GPIO port signals are not explicitly mapped to a device pin, the inputs will continue
to monitor the pin while outputs are disconnected. For example, when the Key Matrix block
has control of the ROW pins, GPIO port C inputs still monitor the state of the ROW pins.
Another level of functional muxing is applied to several EGPIO pins. The Syscon DeviceCfg
register bits RonG, MonG, TonG, HC3EN, HC1EN, and map different functionality to the
EGPIO pins:
Some GPIO signals are used as inputs by other functional blocks. EGPIO[2:1] are routed to
the DMA controller to allow for external DMA requests. IDE interface input signals DMARQ
and DASPn are EGPIO[2] and EGPIO[15], respectively.
Note: The various functional modes described in
• MonG maps RI (modem Ring Indicator) onto EGPIO[0].
• RonG maps CLK32K, the 32 KHz clock monitor output for RTC calibration, onto
• TonG maps TENn, the RS485 transmit enable output, onto EGPIO[3].
• Both HC3EN and HC1EN map the synchronous HDLC clock onto EGPIO[3].
10. COL[7:0] are the Key Matrix column pins.
EGPIO[1].
0x8084_000C
0x8084_001C
0x8084_002C
0x8084_003C
0x8084_004C
0x8084_0000
0x8084_0004
0x8084_0008
0x8084_0010
0x8084_0014
0x8084_0018
0x8084_0020
0x8084_0024
0x8084_0028
0x8084_0030
0x8084_0034
0x8084_0038
0x8084_0040
0x8084_0044
0x8084_0048
DeviceCfg register in Syscon. See
register information.
Address
Read Location
GPIOFIntType1
PCDDR
PDDDR
PGDDR
PHDDR
PADDR
PBDDR
PEDDR
PFDDR
PBDR
PCDR
PDDR
PEDR
RSVD
RSVD
PGDR
PHDR
RSVD
PADR
PFDR
Table 28-5. GPIO Register Address Map
Copyright 2007 Cirrus Logic
Chapter
Table 28-4
5,
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
“DeviceCfg” on page 5-25
are selected via bits set in the
Write Location
GPIOFIntType1
PCDDR
PDDDR
PGDDR
PHDDR
PADDR
PBDDR
PEDDR
PFDDR
PBDR
PCDR
PDDR
PEDR
RSVD
RSVD
PGDR
PHDR
RSVD
PADR
PFDR
for additional
EP93xx User’s Guide
Reset Value
GPIO Interface
Note 1
Note 1
Note 1
Note 1
Note 2
Note 1
Note 1
Note 1
0x0C
0x00
0x00
0x00
0x00
0x03
0x00
0x00
0x00
-
-
-
28-9
28
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