EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 395
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 395 of 824
- Download datasheet (13Mb)
DS785UM1
10.1.1 DMA Features List
10.1 Introduction
The DMA Controller can be used to interface streams from 20 internal peripherals to the
system memory using 10 fully-independent programmable channels that consist of 5 Memory
to Internal Peripheral (M2P) transmit channels and 5 Peripheral to Memory (P2M) receive
channels.
The DMA Controller can also be used to interface streams from Memory to Memory (M2M),
from Memory to Internal Peripheral (M2P), or from Memory to External Peripheral (M2P),
using 2 dedicated M2M channels. External handshake signals are optionally available to
support Memory to/from External Peripheral transfers (M2P/P2M). A software trigger is
available for Memory to Memory transfers, and a hardware trigger is available for Memory to
Internal Peripheral.
On the EP93xx chip the following peripherals may be allocated to the 10 channels.
Each peripheral has it’s own bi-directional DMA bus capable of transferring data in both
directions simultaneously. All memory transfers take place via the main system AHB bus.
SSP and IDE can also use the M2M channels to send or receive data using their memory
mapping to perform transfers.
SSPRx, SSPTx, and IDE have access to DMA M2M hardware transfer requests.
DMA specific features are:
• I
• AAC (which contains 3 Tx and 3 Rx DMA Channels)
• UART1 (which contains 1 Tx and 1 Rx DMA Channels)
• UART2 (which contains 1 Tx and 1 Rx DMA Channels)
• UART3 (which contains 1 Tx and 1 Rx DMA Channels)
• IrDA (which contains 1 Tx and 1 Rx DMA Channels)
• Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx
• Two dedicated channels for Memory-to-Memory (M2M) and Memory-to-External
and 5 Rx).
Peripheral Transfers (external M2P/P2M).
2
S (which contains 3 Tx and 3 Rx DMA Channels)
Copyright 2007 Cirrus Logic
10DMA Controller
Chapter 10
10-1
10
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