EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 245
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 245 of 824
- Download datasheet (13Mb)
Blink Control Registers
BlinkRate
BlinkMask
DS785UM1
31
15
31
15
Address: 0x8003_0040
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
Address: 0x8003_0044
Default: 0x0000_0000
Definition: Blink Mask register
30
14
30
14
29
13
29
13
28
12
28
12
RSVD:
RATE:
This register is used in conjunction with the
which pixels that are fetched from SDRAM are blink pixels.
RSVD
RSVD
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Rate - Read/Write
The blink rate value that is written to this field controls the
number of video frames that occur before the LUT
addresses assigned to ‘blink’ change between masked
and unmasked (see
on/off blink cycle is controlled by this equation:
Blink Cycle = 2 x (1/VCLK) x HClkTotal x VLinesTotal x
(255 - BlinkRate)
Raster Engine With Analog/LCD Integrated Timing and Interface
24
24
8
8
MASK
RSVD
23
23
7
7
22
22
6
6
“Blink Function” on page
21
21
5
5
BlinkPattrn
20
20
4
4
MASK
RATE
register to determine
19
19
3
3
EP93xx User’s Guide
18
18
2
2
7-10). The
17
17
1
1
16
16
7-63
0
0
7
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