EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 539
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 539 of 824
- Download datasheet (13Mb)
14.1 Registers
UART Register Descriptions
UART1Data
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
For words to be transmitted:
30
14
• • if the FIFOs are enabled, data written to this location is pushed onto the transmit
29
13
FIFO
• if the FIFOs are not enabled, data is stored in the transmitter holding register (the
bottom word of the transmit FIFO). The write operation initiates transmission from
the UART. The data is prefixed with a start bit, appended with the appropriate parity
bit (if parity is enabled), and a stop bit. The resultant word is then transmitted.
For received words:
• if the FIFOs are enabled, the data byte is extracted, and a 3-bit status (break, frame
and parity) is pushed onto the 11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from the UART1Data register
while the corresponding status information can be read by a successive read of the
UART1RXSts register.
28
12
0x808C_0000 - Read/Write
0x0000_0000
UART Data Register
RSVD:
DATA:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
UART Data: read for receive data, write for transmit data
24
8
RSVD
23
7
UART1 With HDLC and Modem Control Signals
22
6
21
5
20
4
DATA
19
3
EP93xx User’s Guide
18
2
17
1
14-17
16
0
14
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