EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 129
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
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Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 129 of 824
- Download datasheet (13Mb)
DS785UM1
The normal boot function is described in
Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg
register is set. This mode is available for a software configuration option that is readable by
the boot code.
In either normal boot or serial boot mode, once the processor starts up, it will begin to
execute the instruction at logical address 0x0000_0000. Various configuration options are
provided to select a memory device for booting from at address location 0. The options are
listed in
EECLK EEDAT BOOT1
0
0
1
1
1
1
Table
1
1
1
1
1
1
5-2.
0
0
0
0
0
0
BOOT0 ASDO CSn[7:6]
Copyright 2007 Cirrus Logic
0
0
1
0
0
0
Table 5-2. Boot Configuration Options
1
0
1
0
x
x
Chapter 4 on page
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
xx
xx
External boot fusing Sync boot mode and SDCSn3.
The media type must be either SROM or SyncFLASH.
The selection of the bus width is determined by latched
CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
Internal boot from UART1.
Internal SPI boot if HeaderID is found.
Internal boot using Sync boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
See memory map in
boot mode.
Internal boot using Async boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
See memory map in
ASYNC boot mode.
4-1.
Boot Configuration
Table 2-7 on page 2-16
Table 2-7 on page 2-16
EP93xx User’s Guide
System Controller
for SYNC
for
5-3
5
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