EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 303
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 303 of 824
- Download datasheet (13Mb)
DS785UM1
9.1.1 Detailed Description
9.1.1.1 Host Interface and Descriptor Processor
9.1 Introduction
The Ethernet LAN Controller incorporates all the logic needed to interface directly to the AHB
and to the Media Independent Interface (MII). It includes local memory and DMA control, and
supports full duplex operation with flow control support.
diagram.
This block was designed with a RAM of 544 words, each word containing 33 bits. These
RAMs are used for packet buffering and controller data storage. One RAM is dedicated to the
receiver, and one dedicated to the transmitter. These RAMs are mapped into the register
space and are accessible via the AHB.
The Host Interface can be functionally decomposed into the AHB Interface Controller and the
Descriptor Processor. The AHB Interface Controller implements the actual connection to the
AHB. The controller responds as a AHB bus slave for register programming, and acts as an
AHB bus master for data transfers.
AHB
AHB
Interface
1/10/100 MBPS Ethernet LAN Controller
Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram
TX/RX
Descriptor
Processors
91/10/100 Mbps Ethernet LAN Controller
Copyright 2007 Cirrus Logic
MAC
Reconciliation
Sub-layer
Figure 9-1
MII
shows a simplified block
1/10/100
Mbit
Phy
(External)
Chapter 9
9-1
9
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