EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 517
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 517 of 824
- Download datasheet (13Mb)
BootSts
DS785UM1
31
15
Definition:
Bit Descriptions:
Address: 0x8006_000C - Read Only
Default: 0x0000_0000
Definition:
Bit Descriptions:
30
14
29
13
28
12
The Refresh Timer register is used to specify the period between refresh
cycles.
RSVD:
Refcnt:
When power on reset is asserted, the values of the boot mode option pins
shown in
latched values. This register can be read to determine which memory
configuration was used during the boot process.
RSVD:
ASDO:
Width:
27
11
Table 13-1
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. - Unknown During Read
Refresh Count - Read/Write
The value written to this field specifies, in multiples of the
period of HCLK, the time period between refresh cycles.
For example, if the period of HCLK is 20 ns, this field
should be written to 0x320 (decimal 800) to generate a
16 ms refresh period. On reset, this field defaults to
0x0080 (decimal 128) to generate a 2.56 ms refresh
period, but it must be written during the SDRAM
initialization routine to the appropriate value for the
SDRAM devices. If this field is written to 0x0000, no
refresh cycles are issued.
Reserved - Unknown During Read
Latched ASDO pin value - Read Only
Boot Media:
1 - SyncROM or SyncFLASH
0 - Asynchronous ROM
Boot memory bus Width - Read Only
are latched. The Boot Status register reflects those
24
8
RSVD
23
7
22
6
SDRAM, SyncROM, and SyncFLASH Controller
21
5
20
4
19
3
Latched
EP93xx User’s Guide
ASDO
18
2
17
1
Width
13-21
16
0
13
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