ACE1501EN Fairchild Semiconductor, ACE1501EN Datasheet - Page 8

• Manufacturer Part Number: ACE1501EN
• Description: IC MCU 1KBIT EEPROM 8DIP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 15xxr

Specifications of ACE1501EN

• Core Processor: ACE1502
• Core Size: 8-Bit
• Speed: 25MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1501 Product Family Rev. 1.1
3. Arithmetic Controller Core
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting and block
encryption. It is based on a modified Harvard architecture
meaning peripheral, I/O, and RAM locations are addressed sep-
arately from instruction data.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This
allows the X-pointer (12-bits) to point to any memory location in
either segment of the memory map. This modification improves
Figure 12. Programming Model
3.1.1 Accumulator (A)
The Accumulator is a general-purpose 8-bit register that is used
to hold data and results of arithmetic calculations or data manip-
ulations.
3.1.2 X-Pointer (X)
The X-Pointer register allows for a 12-bit indexing value to be
added to an 8-bit offset creating an effective address used for
reading and writing between the entire memory space. (Soft-
ware can only read from code EEPROM.) This provides soft-
ware with the flexibility of storing lookup tables in the code
EEPROM memory space for the core’s accessibility during nor-
mal operation.
The ACEx core allows software to access the entire 12-bit X-
Pointer register using the special X-pointer instructions e.g. LD
X, #000H. (See Table 8.) However, software may also access
the register through any of the memory-mapped instructions
using the XHI (X[11:8]) and XLO (X[7:0]) variables located at
0xBE and 0xBF, respectively. (See Table 10.)
The X register is divided into two sections. The 11 least signifi-
cant bits (LSBs) of the register is the address of the program or
data memory space. The most significant bit (MSB) of the reg-
ister is write only and selects between the data (0x000 to
0x0FF) or program (0x800 to 0xFFF) memory space.
Example: If Bit 11 = 0, then the LD A, [00,X] instruction will take
a value from address range 0x000 to 0x0FF and load it into A. If
A
X
PC
SP
SR
11
10
R
7
0 0
G
Z
C
3
8
H
the overall code efficiency of the ACEx microcontroller and
takes advantage of the flexibility found on Von Neumann style
machines.
3.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Pro-
gram Counter (PC), Stack Pointer (SP), and Status Register
(SR). The X, SP, and SR registers are all memory-mapped.
Bit 11 = 1, then the LD A, [00,X] instruction will take a value
from address range 0x800 to 0xFFF and load it into A.
The X register can also serve as a counter or temporary storage
register. However, this is true only for the 11-LSBs since the
12
3.1.3 Program Counter (PC)
The 11-bit program counter register contains the address of the
next instruction to be executed. After a reset, if in normal mode
the program counter is initialized to 0x800.
3.1.4 Stack Pointer (SP)
The ACEx microcontroller has an automatic program stack with
a 4-bit stack pointer. The stack can be initialized to any location
between addresses 0x30-0x3F. Normally, the stack pointer is
initialized by one of the first instructions in an application pro-
gram. After a reset, the stack pointer is defaulted to 0xF pointing
to address 0x3F.
The stack is configured as a data structure which decrements
from high to low memory. Each time a new address is pushed
onto the stack, the core decrements the stack pointer by two.
Each time an address is pulled from the stack, the core incre-
ments the stack pointer is by two. At any given time, the stack
pointer points to the next free location in the stack.
When a subroutine is called by a jump to subroutine (JSR)
instruction, the address of the instruction is automatically
pushed onto the stack least significant byte first. When the
N
0
0
0
0
th
bit is dedicated for memory space selection.
8-bit accumulator register
12-bit X pointer register
11-bit program counter
4-bit stack pointer
8-bit status register
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag (bit 4)
GLOBAL INTERRUPT enable
READY flag (from EEPROM)
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