ACE1501EN Fairchild Semiconductor, ACE1501EN Datasheet
ACE1501EN
Specifications of ACE1501EN
Related parts for ACE1501EN
ACE1501EN Summary of contents
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... G3 G4 (TX 100nf Decoupling capacitor recommended 2. Available only in the 14-pin package option ©2002 Fairchild Semiconductor Corporation ACE1501 Product Family Rev. 1.1 I On-chip oscillator — No external components — 1µs instruction cycle time +/-2% accuracy I Instruction set geared for block encryption I On-chip Power-on Reset I Programmable read and write disable functions ...
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Figure 2. ACEx Application Example (Remote Keyless Entry) Optional LED Figure 3. ACE1501 8-pin SOIC and DIP Device Pinout a) Normal Mode Operation G3 VCC GND Figure ...
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Electrical Characteristics Absolute Maximum Ratings Ambient Storage Temperature Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins Part Number ACE1501E ACE1501V ACE1501 DC Electrical Characteristics, All measurements are valid for ambient operating temperature unless otherwise stated. Symbol ...
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ACE1501 AC Electrical Characteristics, All measurements are valid for ambient operating temperature unless otherwise stated. Parameter Instruction cycle time from internal clock - setpoint Internal clock frequency variation Crystal oscillator frequency External clock frequency EEPROM write time Internal clock start ...
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AC & DC Electrical Characteristic Graphs The graphs in this section are for design guidance and are based on preliminary test data. Figure 6. Internal Oscillator Frequency 2.01 2 1.99 1.98 1.97 1.96 1.95 1.94 1.93 Figure 7. LBD and ...
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Figure 8. Icc Active 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 Figure 9. HALT Mode Currents 20.000 18.000 16.000 14.000 12.000 10.000 8.000 6.000 4.000 2.000 0.000 ...
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Figure 10. IDLE Mode Currents 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 Figure 11 vs. Current OL OH 3.00 2.50 2.00 1.50 1.00 0.50 0.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 ACE1501 Product ...
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Arithmetic Controller Core The ACEx microcontroller core is specifically designed for low cost applications involving bit manipulation, shifting and block encryption based on a modified Harvard architecture meaning peripheral, I/O, and RAM locations are addressed sep- arately ...
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The RET instruction pulls the previously stacked return address from the stack and loads it into the program counter. Execution then continues at the recovered return address. 3.1.5 Status ...
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Addressing Modes The ACEx microcontroller has seven addressing modes indexed, indirect, direct, immediate, absolute jump, and relative jump. Indexed The instruction allows an 8-bit unsigned offset value to be added to the 11-LSBs of the X-pointer yielding a new ...
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Table 9. Instruction Cycles and Bytes Mnemonic Operand Bytes ADC A, [X] 1 ADC A, [#,X] 2 ADC ADC ADD A, [X] 1 ADD A, [#,X] 2 ADD ADD A, # ...
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Memory Map All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory space. Table 10. Memory Mapped Registers Address Memory Space 0x00 - 0x3F 0x40 - 0x7F 0x80-0x9F 0xA0 ...
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Memory The ACEx microcontroller has 64 bytes of SRAM and 64 bytes of EEPROM available for data storage. The device also has 1K bytes of EEPROM for program storage. Software can read and write to SRAM and data EEPROM ...
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Table 11. Timer 1 Control Register (T1CNTRL) T1CNTRL Register Bit Name Bit 7 T1C3 Bit 6 T1C2 Bit 5 T1C1 Bit 4 T1C0 Bit 3 T1PND Bit 2 T1EN Bit 1 M1S1 Bit 0 T1RBEN Table 12. Timer 1 Operating ...
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The following steps show how to properly configure Timer 1 to operate in the PWM mode. For this example, the T1 output sig- nal is toggled with every timer underflow and the “high” and “low” times for the T1 output ...
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Write the appropriate control value to the T1CNTRL register to select External Event Counter mode, to clock every falling edge, to set the enable bit, to clear the pending flag, and to start the counter. (See Table 11 and ...
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Table 11 and Table 12 T1CNTRL, #64H ; T1C1 is the edge select bit 6. As soon as the input capture mode is enabled, the timer starts counting. When the selected edge is sensed on T1, the ...
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Watchdog The Watchdog timer is used to reset the device and safely recover in the rare event of a processor “runaway condition.” The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer. The Watchdog timer must be ...
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The OCFLAG signal is read only and goes high when the last encoded bit of the DAT0 frame is transmitting. The OCFLAG sig- nal is used to inform software that the DAT0 frame transmission operation is completing (see Figure 25). ...
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Figure 22. Bit Period Configuration (BPSEL) Register Bit 7 Bit Figure 23. HBC Control (HBCNTRL) Register Bit 7 Bit 6 OCFLAG IOSEL START / STOP Figure 24. HBC signals for one byte message in PWM format Condition: ...
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Multi-Input Wakeup/Interrupt Block The Multi-Input Wakeup (MIW)/Interrupt memory-mapped registers associated with this circuit: WKEDG (Wakeup Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending). Each register has 8-bits with each bit corresponding to an input pins as shown in Figure ...
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Figure 27. Multi-input Wakeup (MIW) Block Diagram G0 G7 WKEDG[0:7] 10. WKINTEN: Bit 7 of T0CNTRL 9. I/O Port The eight I/O pins (six on 8-pin package option) are bi- directional (see Figure 28). The bi-directional I/O pins can be ...
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In-circuit Programming Specification The ACEx microcontroller supports in-circuit programming of the internal data EEPROM, code EEPROM, and the initializa- tion registers. In order to enter into program mode a 10-bit opcode (0x34B) must be shifted into the ACE1501 while ...
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Figure 30. Programming Protocol VCC T reset RESET LOAD (G3) CLOCK (G1) SHIFT_IN (G4 10-bit Opcode = 0x34B SHIFT_OUT (G2) (in write mode) SHIFT_OUT (G2) (in read mode) 13. During in-circuit programming, ...
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Brown-out Reset The Brown-out Reset (BOR) function is used to hold the device in reset when Vcc drops below a fixed threshold (1.83V.) While in reset, the device is held in its initial condition until Vcc rises above the ...
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Table 15. LBD Control Register Definition Bit 7 Bit 6 Level BL[4] BL[ ...
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RESET block When a RESET sequence is initiated, all I/O registers will be reset setting all I/Os to high-impedence inputs. The system clock is restarted after the required clock start-up delay. A reset is generated by any one of ...
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Figure 36. Recommended HALT Flow Normal Mode LD HALT, #01H Multi-Input HALT Mode Wakeup LD PMC, #00H Resume Normal Mode 16. IDLE Mode In addition to the HALT mode power saving feature, the device also supports an IDLE mode operation. ...
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... Part Number ACE1501EM8 X X ACE1501EM8X X X ACE1501EM X X ACE1501EMX X X ACE1501EMT8 X X ACE1501EMT8X X X ACE1501EMT X X ACE1501EMTX X X ACE1501EN X X ACE1501EN14 X X ACE1501VM8 X X ACE1501VM8X X X ACE1501VM X X ACE1501VMX X X ACE1501VMT8 X X ACE1501VMT8X X X ACE1501VMT X X ACE1501VMTX X X ACE1501VN X X ACE1501VN14 ...
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... NOM (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.045 ± 0.015 (1.143 ± 0.381) 0.060 (1.524) 0.050 (1.270) 8-Pin DIP (N) Order Number ACE1501EN/ACE1501VN Package Number N08A 30 0.189 - 0.197 (4.800 - 5.004 Lead #1 IDENT 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0 ...
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Physical Dimensions inches (millimeters) unless otherwise noted) 0.246 - 0.256 (6.25 - 6.5) 0.123 - 0.128 (3.13 - 3.30) 0.0433 (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 Order Number ACE1501EMT8/ACE1501VMT8 ...
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... All leads Seating Plane 0.014 0.016 - 0.050 0.050 (0.356) (1.270) (0.406 - 1.270) Typ. All Leads Typ Molded Small Out-Line Package (M) Order Number ACE1501EM/ACE1501EM Package Number M14A 14-Pin DIP (N14) Order Number ACE1501EN14/ACE1501VN14 Package Number N14A 32 0.335 - 0.344 (8.509 - 8.788 0.010 Max. (0.254 ...
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... Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support ...