ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 297
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 26-1. Block Diagram
26.3
2549M–AVR–09/10
TDI
TDO
TCK
TMS
TAP - Test Access Port
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
•
•
•
•
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
DECODER
ADDRESS
TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine.
TCK: Test Clock. JTAG operation is synchronous to TCK.
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
ATmega640/1280/1281/2560/2561
UNIT
BOUNDARY SCAN CHAIN
PC
Instruction
JTAG / AVR CORE
COMMUNICATION
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
PERIPHERIAL
ANALOG
UNITS
Control & Clock lines
Analog inputs
297
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