ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 205
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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21. USART
21.1
Overview
2549M–AVR–09/10
Features
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
The ATmega640/1280/2560 has four USART’s, USART0, USART1, USART2, and USART3.
The functionality for all four USART’s is described below. USART0, USART1, USART2, and
USART3 have different I/O registers as shown in
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in
page 56
The Power Reducion USART1 bit, PRUSART1, in
page 57
The Power Reducion USART2 bit, PRUSART2, in
page 57
The Power Reducion USART3 bit, PRUSART3, in
page 57
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
ATmega640/1280/1281/2560/2561
“Register Summary” on page
“PRR0 – Power Reduction Register 0” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
Figure 21-1 on page
410.
206. CPU
205
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