PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 13

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in
TABLE 2-1
Legend:
Note 1:
Address Name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Bank 0
1999 Microchip Technology Inc.
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2:
3:
4:
5:
Table
SPECIAL FUNCTION REGISTERS
PORTC
TMR1L
TMR1H
T1CON
TMR2
T2CON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
These registers/bits are not implemented on the 28-pin devices read as '0'.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
2-1.
PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
PORTC Data Latch when written: PORTC pins when read
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
USART Transmit Data Register
USART Receive Data Register
A/D High Byte Result Register
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTD Data Latch when written: PORTD pins when read
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
PSPIF
ADCS1
WCOL
LVDIF
SPEN
Bit 7
IRP
GIE
—
—
—
—
—
—
—
(3)
TOUTPS3
SSPOV
ADCS0
PEIE
ADIF
Bit 6
RP1
RX9
—
—
—
—
—
—
—
PORTA5
T1CKPS1
TOUTPS2
SSPEN
CCP1X
CCP2X
SREN
CHS2
RCIF
Bit 5
RP0
T0IE
Advance Information
—
—
—
(5)
PORTA Data Latch when written: PORTA<4:0> pins when read
Write Buffer for the upper 5 bits of the Program Counter
TOUTPS1
T1CKPS0
CCP1Y
CCP2Y
CREN
CHS1
INTE
Bit 4
TXIF
CKP
TO
—
–
T1OSCEN
TOUTPS0
CCP1M3
CCP2M3
ADDEN
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
SSPM3
SSPIF
BCLIF
CHS0
Bit 3
RBIE
PD
—
GO/DONE
TMR2ON
CCP1M2
CCP2M2
T1SYNC
CCP1IF
SSPM2
FERR
Bit 2
RE2
T0IF
—
Z
T2CKPS1
TMR1CS
CCP1M1
CCP2M1
TMR2IF
SSPM1
OERR
CHS3
INTF
Bit 1
RE1
DC
—
PIC16C77X
T2CKPS0
TMR1ON
CCP1M0
CCP2M0
TMR1IF
CCP2IF
SSPM0
ADON
RX9D
Bit 0
RBIF
RE0
C
DS30275A-page 13
Value on:
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 11xx
xxxx xxxx
xxxx xxxx
0000 000x
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
-000 0000
--0x 0000
--00 0000
--00 0000
--00 0000
---0 0000
---- -000
0--- 0--0
POR,
BOR
other resets
Value on all
0000 0000
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 000u
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 000x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu 11uu
-000 0000
--0u 0000
--uu uuuu
--00 0000
--00 0000
---0 0000
---- -000
0--- 0--0
(2)