PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 104

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C77X
9.2.2
The receiver block diagram is shown in
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates at
the bit rate or at F
The USART module has a special provision for multi-
processor communication. When the RX9 bit is set in
the RCSTA register, 9-bits are received and the ninth bit
is placed in the RX9D status bit of the RSTA register.
The port can be programmed such that when the stop
bit is received, the serial port interrupt will only be acti-
vated if the RX9D bit = 1. This feature is enabled by
setting the ADDEN bit RCSTA<3> in the RCSTA regis-
ter. This feature can be used in a multi-processor sys-
tem as follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for
a data byte). If the ADDEN bit is set in the slave’s
RCSTA register, all data bytes will be ignored. How-
ever, if the ninth received bit is equal to a ‘1’, indicating
that the received byte is an address, the slave will be
interrupted and the contents of the RSR register will be
transferred into the receive buffer. This allows the slave
to be interrupted only by addresses, so that the slave
can examine the received byte to see if it is addressed.
The addressed slave will then clear its ADDEN bit and
prepare to receive data bytes from the master.
When ADDEN is set, all data bytes are ignored. Fol-
lowing the STOP bit, the data will not be loaded into the
receive buffer, and no interrupt will occur. If another
byte is shifted into the RSR register, the previous data
byte will be lost.
The ADDEN bit will only take effect when the receiver
is configured in 9-bit mode.
The receiver block diagram is shown in
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
DS30275A-page 104
USART ASYNCHRONOUS RECEIVER
OSC
.
Figure
Figure
Advance Information
9-6. The
9-6.
9.2.3
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
• Enable the asynchronous serial port by clearing
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is com-
• Read the RCSTA register to get the ninth bit and
• Read the 8-bit received data by reading the
• If any error occurred, clear the error by clearing
• If the device has been addressed, clear the
baud rate. If a high speed baud rate is desired, set
bit BRGH.
bit SYNC and setting bit SPEN.
plete, and an interrupt will be generated if enable
bit RCIE was set.
determine if any error occurred during reception.
RCREG register, to determine if the device is
being addressed.
enable bit CREN.
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
1999 Microchip Technology Inc.