PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 264

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

PIC17C7XX
FIGURE 20-23:
TABLE 20-19: A/D CONVERSION REQUIREMENTS
DS30289B-page 264
Note 1: ADRES register may be read on the following T
Param.
130
131
132
134
No.
Note 1: If the A/D clock source is selected as RC, a time of T
A/D DATA
†
SAMPLE
A/D CLK
2:
ADRES
BSF ADCON0, GO
ADIF
Data in “Typ” column is at 5V, 25 C unless otherwise stated.
See Section 16.1 for minimum conditions when input voltage has changed more than 1 LSb
T
T
GO
Sym
T
Q4
T
CNV
ACQ
AD
GO
SLEEP instruction to be executed.
A/D clock period
Conversion time
(not including acquisition time) (Note 1)
Acquisition time
Q4 to ADCLK start
132
A/D CONVERSION TIMING
Characteristic
(T
OSC
/2)
9
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
(1)
8
OLD_DATA
7
CY
SAMPLING STOPPED
cycle.
(Note 2)
. . .
Min
1.6
3.0
2.0
3.0
10
11
—
CY
131
130
is added before the A/D clock starts. This allows the
. . .
Tosc/2
Typ†
4.0
6.0
—
—
—
20
—
2
Max
6.0
9.0
—
—
12
—
—
—
1
Units
Tad
—
1 T
0
s
s
s
s
s
s
2000 Microchip Technology Inc.
CY
T
T
A/D RC mode
A/D RC mode
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on C
If the A/D clock source is
selected as RC, a time of
T
clock starts. This allows the
SLEEP instruction to be
executed.
.
OSC
OSC
CY
NEW_DATA
is added before the A/D
DONE
based, V
based, V
Conditions
HOLD
REF
REF
).
full range
3.0V