PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 105

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

13.1.2
To select 16-bit mode, set the T16 bit. In this mode,
TMR2 and TMR1 are concatenated to form a 16-bit
timer (TMR2:TMR1). The 16-bit timer increments until
it matches the 16-bit period register (PR2:PR1). On the
following timer clock, the timer value is reset to 0h, and
the TMR1IF bit is set.
When selecting the clock source for the 16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care”, however, ensure that
TMR2ON is set (allows TMR2 to increment). When
TMR1CS is clear, the timer increments once every
instruction cycle (F
timer increments on every falling edge of the RB4/
TCLK12 pin. For the 16-bit timer to increment, both
TMR1ON and TMR2ON bits must be set (Table 13-2).
TABLE 13-2:
FIGURE 13-2:
T16 TMR2ON TMR1ON
1
1
1
0
2000 Microchip Technology Inc.
RB4/TCLK12
1
0
x
1
TIMER1 AND TIMER2 IN 16-BIT
MODE
TURNING ON 16-BIT TIMER
OSC
1
1
0
1
TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE
F
/4). When TMR1CS is set, the
Set Interrupt TMR1IF
OSC
TMR1CS
(TCON1<0>)
(PIR1<4>)
/4
16-bit timer
(TMR2:TMR1) ON
Only TMR1 increments
16-bit timer OFF
Timers in 8-bit mode
0
1
Result
(TCON2<0>)
TMR1ON
RESET
Equal
TMR2 x 8
PR2 x 8
13.1.2.1
When TMR1CS is set, the 16-bit TMR2:TMR1 incre-
ments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchro-
nized by the internal phase clocks twice every instruc-
tion cycle. This causes a delay from the time a falling
edge
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
MSB
Comparator x16
Comparator<8>
appears
External Clock Input for
TMR2:TMR1
TMR1 x 8
PR1 x 8
on
LSB
RB4/TCLK12
PIC17C7XX
DS30289B-page 105
to
the
time