PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 146

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

PIC17C7XX
15.2.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then
SCL pin should be enabled by setting bit CKP
(SSPCON1<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 15-13).
FIGURE 15-12:
FIGURE 15-13:
DS30289B-page 146
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S
S
A7 A6 A5 A4 A3 A2 A1
1
Slave Transmission
A7
2
1
Data in
sampled
Receiving Address
3
A6
2
I
I
2
4
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
3
5
A4
4
6
7
A3
5
R/W = 0
8
A2
ACK
6
9
A1
7
D7
1
R/W = 1
D6
2
8
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
9
ACK
responds to SSPIF
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
SCL held low
while CPU
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the not ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, the SCL pin
should be enabled by setting the CKP bit.
D1
7
D7
1
SSPBUF is written in software
D0
8
ACK
D6
9
Cleared in software
2
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D7
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
5
4
 2000 Microchip Technology Inc.
ACK is not sent.
D3
D2
5
6
D2
6
From SSP Interrupt
Service Routine
D1
7
D1
7
D0
8
D0
8
Not ACK
R/W = 0
ACK
Not
9
9
Bus Master
Transfer
Terminates
P
P