PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 23

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

5.0
The PIC17CXXX differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR Reset
• WDT Reset
Some registers are not affected in any RESET condi-
tion, their status is unknown on POR and unchanged in
any other RESET. Most other registers are forced to a
“RESET state”. The TO and PD bits are set or cleared
differently in different RESET situations, as indicated in
Table 5-3. These bits, in conjunction with the POR and
BOR bits, are used in software to determine the nature
of the RESET. See Table 5-4 for a full description of the
RESET states of all registers.
FIGURE 5-1:
2000 Microchip Technology Inc.
MCLR
OSC1
V
† This RC oscillator is shared with the WDT when not in a power-up sequence.
DD
RESET
RC OSC†
OST/PWRT
On-chip
V
Module
Module
Detect
DD
WDT
BOR
Rise
OST
PWRT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
10-bit Ripple Counter
10-bit Ripple Counter
Brown-out
Power_On_Reset
Reset
Time_Out
Reset
WDT
External
Reset
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
(Enable the PWRT timer
only during POR or BOR)
Note:
While the device is in a RESET state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
PIC17C7XX
S
R
DS30289B-page 23
Q
Chip_Reset