UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 589

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UPD70F3735GK-GAK-AX

Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GK-GAK-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
The communication reservation flowchart is illustrated below.
(Communication reservation)
Note The communication reservation operation executes a write to the IICn register when a stop
Remark
condition interrupt request occurs.
n = 0, 1
Yes
Note
Figure 17-16. Communication Reservation Flowchart
Cancel communication
reservation
Define communication
reservation
IICn register
MSTSn bit = 0?
SET1 STTn
Wait
DI
EI
No
(Generate start condition)
xxH
Sets STTn bit (communication reservation).
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM).
Secures wait period set by software (see Table 17-16).
Confirmation of communication reservation
Clears user flag.
IICn register write operation
CAPTER 17 I
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C BUS

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