UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 242
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3735GK-GAK-AX
Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3735GC-GAD-AX.pdf
(835 pages)
Specifications of UPD70F3735GK-GAK-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 242 of 835
- Download datasheet (5Mb)
V850ES/JF3-L
PWM waveform from the TOPn1 pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
Remark
Active level width = (Set value of TPnCCR1 register ) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
CCR0 buffer register
CCR1 buffer register
n = 0 to 2, 5, m = 0, 1
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
NTTPnCC0 signal
TOPn0 pin output
TOPn1 pin output
16-bit counter
TPnCE bit
FFFFH
0000H
Figure 7-25. Basic Timing in PWM Output Mode
Active period
D
(D
10
D
10
00
)
(D
D
D
Cycle
00
10
D
00
D
D
10
10
D
+ 1)
00
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
00
D
Inactive period
(D
10
D
00
00
− D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01
Page 226 of 816
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