UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 252

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UPD70F3735GK-GAK-AX

Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GK-GAK-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal
(INTTPnCCm) is generated.
generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
Remark
n = 0 to 2, 5
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function)
TPnCE bit
FFFFH
0000H
D
00
D
CLR instruction
Cleared to 0 by
10
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
00
D
D
01
10
D
11
CLR instruction
Cleared to 0 by
D
D
01
02
D
11
D
12
CLR instruction
Cleared to 0 by
D
02
D
03
D
12
D
13
D
03
D
13
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