UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 176

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UPD70F3735GK-GAK-AX

Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GK-GAK-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock oscillator stop control
(4) Internal oscillator
(5) Prescaler 1
(6) Prescaler 2
(7) Prescaler 3
(8) PLL
Connecting the ceramic/crystal resonator to the X1 and X2 pins, the main clock oscillator oscillates to generates
the following frequencies (f
• In clock-through mode
• In PLL mode
The external clock of the following frequency can be input to the X1 pin.
• In clock-through/PLL mode
The sub-resonator oscillates a frequency of 32.768 kHz (f
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
Oscillates a frequency (f
This prescaler generates the clock (f
TMP0 to TMP2, TMP5, TMQ0, TMM0, CSIB0 to CSIB2, UARTA0 to UARTA2, I
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
and internal system clock (f
f
This circuit divides the clock generated by the main clock oscillator (f
supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
is output. These modes can be selected by using the PLLCTL.SELPLL bit.
Whether the clock is multiplied by 4 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the
PLLCTL.PLLON bit.
CLK
f
f
f
X
X
X
is the clock supplied to the INTC, ROM, RAM, and DMA blocks, and can be output from the CLKOUT pin.
= 2.5 to 10 MHz
= 2.5 to 5 MHz
= 2.5 to 5 MHz
R
) of 220 kHz (TYP.).
X
CLK
).
).
XX
).
XX
XX
to f
to f
XX
XX
/1,024) to be supplied to the following on-chip peripheral functions:
/32) is supplied to the selector that generates the CPU clock (f
X
CHAPTER 6 CLOCK GENERATION FUNCTION
XT
is output as is, and PLL mode in which a multiplied clock
).
X
X
) to a specific frequency (32.768 kHz) and
) by 4.
2
C00, I
2
C01, ADC, DAC, and WDT2
Page 160 of 816
CPU
)

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