HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 826

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 LCD Controller
Bits 4 to 0—Denominator of Clock Division Ratio (DCDR4 to DCDR0): Set denominator of
the input clock division ratio.
Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
Note: The access size indicates the size the CPU uses to access (read from or write to) the
25.2.2
LDMTR sets the control signals output from this LCDC and the polarity of the data signals,
according to the polarity of the signals for the LCD module connected to the LCDC.
Bits 11, 7, and 6—Reserved
Bit 15—FLM (Vertical Sync Signal) Polarity Select (FLMPOL): Selects the polarity of the
FLM (vertical sync signal, first line marker) for the LCD module.
Bit 15
FLMPOL
0
1
Rev.6.00 Mar. 27, 2009 Page 768 of 1036
REJ09B0254-0600
DCDR[4:0]
00001
00010
00100
01000
10000
Initial value:
R/W:
Bit:
register. When accessing this register in a size other than the displayed one, LCDC
operation is not guaranteed.
Only 0 can be written to a reserved bit.
When a setting not allowed is made, e.g. a reserved bit is written to, though the LCDC
operates with its initial values, normal operation is not guaranteed.
This is the common rule to all registers in this LCDC.
LCDC Module Type Register (LDMTR)
FLM
POL
R/W
15
0
Description
FLM pulse is high active
FLM pulse is low active
POL
CL1
R/W
14
0
Clock Division Ratio
1/1
1/2
1/4
1/8
1/16
DISP
POL
R/W
13
0
DPOL
R/W
12
0
11
—
R
0
MCNT
R/W
10
0
CNT
R/W
CL1
9
0
I/O Clock Frequency (MHz)
50.000
50.000
25.000
12.500
6.250
3.125
CNT
CL2
R/W
8
1
—
R
7
0
—
R
6
0
TYP5
R/W
MIF
5
0
TYP4
R/W
MIF
4
0
TYP3
R/W
MIF
3
1
TYP2
R/W
MIF
2
0
(Initial value)
(Initial value)
TYP1
R/W
MIF
1
0
TYP0
R/W
MIF
0
1