HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 33

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

24.3 Data Storage Format which Required by USB Host Controller........................................ 757
24.4 Data Alignment Restriction of USB Host Controller........................................................ 758
24.5 Restrictions on the Data Transfer of USB Controller ....................................................... 759
24.6 Restrictions on the Software Reset and USB Reset .......................................................... 760
24.7 Notes on Using USB Host with Versions Previous to the SH7727C................................ 760
24.8 Usage Notes of Resume Operation of USB Host Controller (USBH) .............................. 761
Section 25 LCD Controller
25.1 Overview........................................................................................................................... 763
24.2.2 HcControl............................................................................................................. 729
24.2.3 HcCommandStatus .............................................................................................. 732
24.2.4 HcInterruptStatus ................................................................................................. 735
24.2.5 HcInterruptEnable................................................................................................ 737
24.2.6 HcInterruptDisable............................................................................................... 739
24.2.7 HcHCCA.............................................................................................................. 740
24.2.8 HcPeriodCurrentED............................................................................................. 740
24.2.9 HcControlHeadED............................................................................................... 741
24.2.10 HcControlCurrentED ........................................................................................... 741
24.2.11 HcBulkHeadED ................................................................................................... 741
24.2.12 HcBulkCurrentED................................................................................................ 742
24.2.13 HcDoneHead........................................................................................................ 742
24.2.14 HcFmInterval ....................................................................................................... 743
24.2.15 HcFmRemaining .................................................................................................. 744
24.2.16 HcFmNumber ...................................................................................................... 745
24.2.17 HcPeriodicStart .................................................................................................... 746
24.2.18 HcLSThreshold .................................................................................................... 746
24.2.19 HcRhDescriptorA ................................................................................................ 747
24.2.20 HcRhDescriptorB................................................................................................. 749
24.2.21 HcRhStatus .......................................................................................................... 750
24.2.22 HcRhPortStatus[1:2] ............................................................................................ 751
24.3.1 Storage Format of the Transferred Data............................................................... 757
24.3.2 Storage Format of the Descriptor......................................................................... 758
24.4.1 Restriction on the Line Boundary of the Synchronous DRAM ........................... 758
24.4.2 Restriction on the Memory Access Address ........................................................ 759
24.5.1 Restriction of the Data Size in IN Transfer.......................................................... 759
24.5.2 Restrictions on the Hub Connection on NAK/STALL Reception ....................... 759
24.5.3 Restrictions when a Low-Speed Device is Disconnected .................................... 760
25.1.1 Features................................................................................................................ 763
25.1.2 Block Diagram..................................................................................................... 764
25.1.3 Pin Configuration................................................................................................. 765
25.1.4 Register Configuration......................................................................................... 765
............................................................................................... 763
Rev.6.00 Mar. 27, 2009 Page xxxi of lvi
REJ09B0254-0600