HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 259

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
Response
time
Icyc:
Bcyc: Duration of one CKIO cycle.
Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules.
Notes: 1. S also includes the memory access wait time.
Duration of one cycle of internal clock supplied to CPU.
2. The internal clock: CKIO: peripheral clock ratio is 2:1:1.
3. The internal clock: CKIO: peripheral clock ratio is 4:1:1.
4. IRQ mode
5. Modules: TMU, RTC, SCI, WDT, REFC
6. Modules: DMAC, ADC, SCIF, LCDC, PCC, USB host, USB function, AFE interface
Total
Minimum
case *
Maximum
case *
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2
3
NMI
(5.5 + X)
× Icyc + 0.5
× Bcyc + 0.5
× Pcyc
7.5
8.5 + S
IRQ
(5.5 + X)
× Icyc + 1
× Bcyc + 4.5
× Pcyc *
16.5
26.5 + S
Number of States
4
PINT
(5.5 + X)
× Icyc + 3.5
× Pcyc *
12.5
18.5 + S
Rev.6.00 Mar. 27, 2009 Page 201 of 1036
5
Section 7 Interrupt Controller (INTC)
Peripheral
Modules
(5.5 + X)
× Icyc + 1.5
× Pcyc *
(5.5 + X)
× Icyc + 3
× Pcyc *
8.5 *
10.5 + S *
16.5 + S *
5
/11.5 *
5
6
5
6
6
Notes
At 60-MHz (CKIO =
30) operation:
0.13–0.28 µs
At 60-MHz (CKIO =
15) operation:
0.26–0.56 µs (in case
of operand cache-hit)
At 60-MHz (CKIO =
15) operation:
0.29–0.59 µs (when
external memory
access is performed
with wait = 0)
REJ09B0254-0600