HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 363

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

For Synchronous DRAM Interface: (see table 12.12)
Bit6:
AMX3
1
0
Values other than above
Notes: 1. Can only be set when using a 16-bit bus width.
2. Can only be set when using a 32-bit bus width.
Bit5:
AMX2
1
1
0
Bit 4:
AMX1
0
1
0
1
0
Bit 3:
AMX0
1
0
0
1
0
1
0
Description
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
(The A11 value is output at A1 when the row address is
output. 8M × 16-bit × 4-bank products) *
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
(The A11 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 512K × 32-bit × 4-bank products)
accessing synchronous DRAM memory.
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 16 bit.
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit. *
The row address begins with A9 when bus width is 16 bit.
Reserved. AMX3 to AMX0 must be set to *1*** before
Reserved (illegal setting)
Rev.6.00 Mar. 27, 2009 Page 305 of 1036
Section 12 Bus State Controller (BSC)
1
REJ09B0254-0600
(Initial value)
2