DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 573
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.2
15.2.1
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Group 0
AN
AN
AN
AN
Bit
ADDRn
Initial value
Read/Write
(n = A to D)
0
1
2
3
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Analog Input Channel
AD9
15
R
0
AD8
14
R
0
Group 1
AN
AN
AN
AN
AD7
4
5
6
7
13
R
0
A/D conversion data
10-bit data giving an
A/D conversion result
AD6
12
R
0
AD5
11
R
0
AD4
10
R
0
AD3
R
9
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD2
R
8
0
AD1
Rev. 3.00 Sep 27, 2006 page 545 of 872
R
7
0
AD0
R
6
0
R
5
0
Section 15 A/D Converter
R
4
0
Reserved bits
R
3
0
REJ09B0325-0300
R
2
0
R
1
0
R
0
0
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