DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 380
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
0
1
2
3
4
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Rev. 3.00 Sep 27, 2006 page 352 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
7
1
6
1
Reserved bits
Function
Enables or disables interrupt requests.
5
1
4
1
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
3
1
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
OVIE
R/W
2
0
IMIEB
R/W
1
0
IMIEA
R/W
0
0
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