DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 214
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Refresh Controller
Pseudo-Static RAM Control Signals
Refresh Cycle Priority Order
When there are simultaneous bus requests, the priority order is:
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion
When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into
bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Rev. 3.00 Sep 27, 2006 page 186 of 872
REJ09B0325-0300
Figure 7.15 shows the control signals for pseudo-static RAM read, write, and refresh cycles.
Address
bus
CS
RD
HWR
LWR
RFSH
AS
Note: * 16-bit access
3
(High)
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
External bus master > refresh controller > DMA controller > CPU
Read cycle
Write cycle *
Area 3 top address
Refresh cycle
(Low)
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